CM3 FPGA Register System IP
CM3 is a Wishbone-based FPGA register and peripheral control system used across Tecphos designs. Manage capability registers, peripheral targets, and multiple controllers in one address space. MIT licensed open source for Tecphos IP customers.
The CM3 system is a controller-based framework for managing multiple capability registers, multiple peripheral targets, and multiple peripheral controllers in FPGA designs.
All Tecphos FPGA designs use CM3 in different configurations to manage status and configuration registers and to interface with I2C and SPI peripherals. CM3 organizes these functions into a single address space so every feature is accessible by the same process.
Why CM3
Most FPGA designs need register maps, peripheral access, and more than one control path (protocol stack, debug, on-board managers). Off-the-shelf CM3 modules provide substantial lift when launching or expanding FPGA systems — without reinventing bus fabric, arbitration, and register plumbing for each project.
Used Across Tecphos IP
Our CoaXPress, GigEVision, and EEVideo IP cores all use CM3 for defined GenICam and feature registers. Customers who license those cores work in the same register model Tecphos uses internally.
Open Source for IP Customers
Tecphos releases the CM3 system as MIT Licensed open source to our IP customers so they can add custom features to their designs on the same foundation.
Configuration-Driven Registers
CM3 uses looping VHDL to implement all registers from a configuration list that specifies:
- Size
- Address
- Access mode
- Default value
Adding a new register is as simple as one configuration line — no new hand-written register code. All register inputs and outputs are collected in a structure, so values are easy to assign and read without adding individual ports at every level of the hierarchy.
Peripheral Targets
Target peripherals are mapped into the same register space using a similar configuration declaration, then connected at the top level. That keeps sensors, PHYs, and other devices on the same map as configuration and status registers.
Multiple Controllers
CM3 supports multiple controller peripherals and arbitrates between them by declaration and connection to the implementation modules. That provides multiple paths for:
- Remote controllers (e.g. GenICam)
- Debug controllers (e.g. a UART)
- On-board controllers (e.g. configuration managers)
…to access the same functions through the same register map.
Wishbone Foundation
CM3 is based on documented Wishbone protocols designed for FPGA data buses. The protocol is well defined, so adding new targets and controllers is a low-risk process. Wishbone was designed to be efficient in FPGA logic.
Highlights
- Single address space for registers, targets, and controllers
- Configuration-list register generation (size, address, access, default)
- Multiple register classes (RO, local update, R/W, set/clear, local reset) and bit-field packing
- Structure-based register I/O — no port explosion through the hierarchy
- Library modules: SPI controller, I2C, UART, SMI/MDIO, dual-port memory, async Wishbone CDC
- Multi-controller arbitration (GenICam, UART debug, on-board managers)
- Wishbone-based, FPGA-efficient bus
- Foundation for Tecphos CoaXPress, GigEVision, and EEVideo GenICam/feature registers
- MIT license for Tecphos IP customers
Datasheet
Related products
- EEVideo FPGA IP — uses CM3 for GenICam and feature registers
- CoaXPress FPGA IP — CM3-backed register model
- GigEVision FPGA IP — CM3-backed register model
- EEVideo Specification and open-source host tools under Products → Open Source
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